1. Field of the Invention
The present invention relates to an exposure system, an exposure method and a semiconductor device manufacturing method for exposing pattern-wise the resist formed on a semiconductor substrate to form a predetermined pattern.
2. Description of the Related Art
In recent years, there have been advances in making structures such as various elements in semiconductor devices yet finer and highly integrated. In order to meet such requirements of being finer and highly integrated, there has been needed the pattern dimension of 200 nm or less and further 100 nm or less, in semiconductor chips during electron-beam exposure, as well as significantly narrow gaps between those patterns.
Recently, to cope with the increase in pattern densities, so-called proximity-effect corrections such as an area-density method are carried out, so as to enable exposure, taking into account influences from surrounding patterns proximate to these patterns (for example, patterns formed within the range of a few micrometers from these patterns). In this case, it is necessary to extremely precisely carry out proximity-effect correction, since there are increased pattern density differences in each pattern alignment, as compared with the case hitherto.
[Patent Document 1] Japanese Patent Application Laid-open No. Hei 11-329961
However, the advances in making structures such as various elements in semiconductor devices yet finer and highly integrated pose difficulties in achieving sufficient exposure correction only with parameters to be empirically determined using samples, as backward scattering factors for the proximity-effect correction.
Patent Document 1 discloses a technique which prepares plural exposure maps of different conditions and types and corrects the amount of exposure on the basis of the exposure maps. However, even with this technique, it is difficult to achieve sufficient exposure correction, in the event of carrying out proximity-effect corrections using the exposure maps, as stated above.